Development of SPICE model of an integral capacitor

Abstract

The article discusses a technique for forming a compact (SPICE) model of an integrated capacitor manufactured using bipolar technology based on the barrier capacitance of one of the junctions of a bipolar transistor. Unlike a discrete analog, an integral capacitor is characterized by a large number of parameters, which is associated with the presence of parasitic resistive and capacitive components. On the basis of the synthesized macromodel, a number of integrated capacitor characteristics were calculated, including capacitance-voltage and frequency dependences of the quality factor. The proposed procedure for synthesizing a compact model of an integrated capacitor can be used to form macromodels of other types of integrated capacitors based on a barrier capacitance, as well as MOS capacitors for dynamic memory and parasitic capacitances of integrated circuit interconnect buses.