Optimization of the functional diagram of the transmitter / receiver via RS-232 interface

Abstract

The article discusses methods for improving the quality of communication in information interaction between devices through the RS-232 data transmission interface by adding HDL logic using the System Verilog hardware description language. The serial interface itself is described in detail, including its operating principle, data packet structure, connection methods with pinout assignments, and an example of message transmission using the specified interface in graphical representation. The results of testing the modified receiver version in the ModelSim environment are presented, using a multiple sampling method to capture data from the transmission line and check for false signals indicating the start of packet transmission, since transmission in the RS-232 interface is performed without synchronized clocking. Experimentally, the optimal time interval for capturing data during signal level establishment was identified. The article also details the modifications made to the receiver and transmitter modules by adding a reset variable that acts as a cycle counter for the receive/send message operation. Additionally, it explains why a transmission speed of 115200 bits per second is popular among industrial and laboratory equipment. The method for obtaining the divider value to set a specialized data transmission speed via the serial interface is described, along with the configuration of the UART chip using configuration registers.